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SOC Design/ Synthesis Engineer

Qualcomm Inc.


Location:
Chennai
Date:
04/23/2018
2018-04-232018-05-23
Job Code:
1963094
Qualcomm Inc.
Apply on the Company Site
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Job Details

Job Title SOC Design/ Synthesis Engineer
Jobid 1963094
Location: Chennai, IND
Job Description:
**Job Id**
E1963094
Job Title
SOC Design/ Synthesis Engineer
Post Date
04/18/2018
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
India - Chennai
Job Overview
Candidate will be responsible for developing next SOC for mobile and adjacent market applications. This role will require the candidate to understand and work on all aspects of VLSI development like micro architecture, logic design, synthesis, formal verification, low power verification, timing analysis, constraints, IO timing closure.
Minimum Qualifications
Must hold a Bachelors and/or a Masters in Electrical Engineering with at least 10+ years experience in Micro architecture definition ,digital logic design and RTL coding.

Good understanding of complex SOC architectures with multiple processors, bus interfaces, peripherals, multimedia engines.

Should have worked on leading technologies 28nm and beyond.

Expertise in AHB and AXI protocols, bus interface is preferable

Experience in ASIC synthesis, timing closure, formal verification, low power verification is a must

Constraints generation, constraint management, constraint validation for SOC

Area, power, performance trade off and optimization

Ability to do complex functional ECO and timing ECO

Understanding of various SOC IO interfaces and timing closure

sound engineering practices in breaking down a problem into its components and solving it

Should have good analytical ability, problem solving skills and be a self-starter

Candidate should be able to lead and work in a team environment

Should be able to manage and lead small to medium sized teams
Preferred Qualifications
Must hold a Bachelors and/or a Masters in Electrical Engineering with at least 10+ years experience in Micro architecture definition ,digital logic design and RTL coding.


Good understanding of complex SOC architectures with multiple processors, bus interfaces, peripherals, multimedia engines.


Should have worked on leading technologies 28nm and beyond.


Expertise in AHB and AXI protocols, bus interface is preferable


Experience in ASIC synthesis, timing closure, formal verification, low power verification is a must


Constraints generation, constraint management, constraint validation for SOC


Area, power, performance trade off and optimization


Ability to do complex functional ECO and timing ECO


Understanding of various SOC IO interfaces and timing closure


sound engineering practices in breaking down a problem into its components and solving it


Should have good analytical ability, problem solving skills and be a self-starter


Candidate should be able to lead and work in a team environment


Should be able to manage and lead small to medium sized teams
Education Requirements
...
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


Apply on the Company Site
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