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Principal Engineer/Manager (RTL Design) -Chennai

Qualcomm Inc.


Location:
Chennai
Date:
04/25/2018
2018-04-252018-05-25
Job Code:
1959008
Qualcomm Inc.
Apply on the Company Site
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Job Details

Job Title Principal Engineer/Manager (RTL Design) -Chennai
Jobid 1959008
Location: Chennai, IND
Job Description:
**Job Id**
E1959008
Job Title
Principal Engineer/Manager (RTL Design) -Chennai
Post Date
03/02/2018
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
India - Chennai
Job Overview
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands


Person will be responsible for developing next generation SoCs for mobile products, automotive and other product categories. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture, platform architecture, front end design, and design convergence. The candidate will need to work with multiple stakeholders in Architecture, Systems, Software, Product and test engineering, various core teams, Verification, DFT, Physical Design teams spread across multi-sites. The candidate will be leading a large team that works on multiple parallel SOC tapeout executions and will need to ensure smooth support through to volume production.


Minimum Qualifications:


-Minimum 15 years of solid experience in SoC design, with experience managing large teams


-Good knowledge of Digital Design and RTL development


-Hands-on experience with SoC Design, Verilog RTL coding


-Working knowledge of front end flows like spyglass lint, CDC, synthesis


-Understanding of Bus protocols (AHB/AXI etc), interconnects, peripherals, DDR, clock & resets


-Understanding of Memory controller designs and Microprocessors is desirable


-Understanding of Chip IO design and packaging is desirable


-Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification


-Manage IP dependencies, planning and tracking of all front end design related tasks


-Driving the project milestones across the design, verification and physical implementations


-Experience in managing a team of talented engineers


-Needs to make effective and timely decisions, even with incomplete information.


-Provides direction, mentoring, and leadership to small to medium sized groups.


-Should possess effective communication and leadership skills


-Good people management, team work skills and strong positive attitude are essential
Minimum Qualifications
Minimum Qualifications:

-Minimum 15 years of solid experience in SoC design, with experience managing large teams

-Good knowledge of Digital Design and RTL development

-Hands-on experience with SoC Design, Verilog RTL coding

-Working knowledge of front end flows like spyglass lint, CDC, synthesis

-Understanding of Bus protocols (AHB/AXI etc), interconnects, peripherals, DDR, clock & resets

-Understanding of Memory controller designs and Microprocessors is desirable

-Understanding of Chip IO design and packaging is desirable

-Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification

-Manage IP dependencies, planning and tracking of all front end design related tasks

-Driving the project milestones across the design, verification and physical implementations

-Experience in managing a team of talented engineers

-Needs to make effective and timely decisions, even with incomplete information.

-Provides direction, mentoring, and leadership to small to medium sized groups.

-Should possess effective communication and leadership skills

-Good people management, team work skills and strong positive attitude are essential
Preferred Qualifications
Minimum Qualifications:


-Minimum 15 years of solid experience in SoC design, with experience managing large teams


-Good knowledge of Digital Design and RTL development


-Hands-on experience with SoC Design, Verilog RTL coding


-Working knowledge of front end flows like spyglass lint, CDC, synthesis


-Understanding of Bus protocols (AHB/AXI etc), interconnects, peripherals, DDR, clock & resets


-Understanding of Memory controller designs and Microprocessors is desirable


-Understanding of Chip IO design and packaging is desirable


-Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification


-Manage IP dependencies, planning and tracking of all front end design related tasks


-Driving the project milestones across the design, verification and physical implementations


-Experience in managing a team of talented engineers


-Needs to make effective and timely decisions, even with incomplete information.


-Provides direction, mentoring, and leadership to small to medium sized groups.


-Should possess effective communication and leadership skills


-Good people management, team work skills and strong positive attitude are essential
Education Requirements
-Masters in Engineering
LI-IND*
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


Apply on the Company Site
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