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Physical Design Engineer (San Diego & Santa Clara, CA)

Qualcomm Inc.


Location:
San Diego, CA
Date:
04/19/2018
2018-04-192018-05-19
Job Code:
1961468
Qualcomm Inc.
Apply on the Company Site
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Job Details

Job Title Physical Design Engineer (San Diego & Santa Clara, CA)
Jobid 1961468
Location: San Diego, CA, 92108, USA
Job Description:
**Job Id**
T1961468
Job Title
Physical Design Engineer (San Diego & Santa Clara, CA)
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
California - San Diego
Overview
Qualcomm's Physical Engineering Team is responsible for the drive and execution of all phases of the complete physical flow for MSM/MDM/CSMs at the core and chip-level. We are actively seeking candidates for multiple Physical positions in San Diego, CA.
**Responsibilities:**

You will be part of a team responsible for the complete Physical Flow for MSM/MDM/CSM chips. Tasks involved can be one or more of the following:
+ Work with the team on understanding in context of physical closure including development of constraints required for implementation.

+ Work with the DFT team on understanding DFT in regards to physical closure.

+ Lead core and Top level closure activities.

+ Develop new scripts/flows to improve the closure process.

+ Complete Physical Implementation of cores i.e. graphics, video, multimedia, processor, DDR.

+ Low-power implementation methods.

+ Core and Top level Floorplanning, placement, CTS, P&R, PV, and Signal Integrity Analysis.

+ Develop high speed customized cells.

**Skills/Experience:**

2+ years of industry experience in the following technical areas:
+ Physical implementation (Floorplanning, CTS, STA) for CPUs and GPUs in advanced technologies.

+ STA tool and closure methodologies

+ Power grid, clock tree, and low-power reduction implementation methods

+ Signal integrity and closure issues such as OCV/AOCV/Statistical

+ Floorplanning, Placement, CTS

+ Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification

+ Programming and scripting skills (Tcl, perl and/or C)

+ Strong verbal and written communication skills **Preferred Qualifications:** 2+ years of industry experience in one or more of the following technical areas:

+ Power-aware yield estimation

+ Vmin optimization

+ Power recovery

+ Technology comparison PPA analysis and sweeps

+ Semicustom of structured blocks

+ Clock tree analysis and optimization

+ Library analysis and evaluations

+ analysis methodologies
Education Requirements
Required: Bachelor's, Computer Engineering, Computer Science and/or Electrical Engineering.

Preferred: Master's, Computer Engineering, Computer Science and/or Electrical Engineering.
\#talentpool
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


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