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Digital Design Engineer - Memory Controller

Qualcomm Inc.


Location:
San Diego, CA
Date:
04/23/2018
2018-04-232018-05-23
Job Code:
1944521
Qualcomm Inc.
Apply on the Company Site
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Job Details

Job Title Digital Design Engineer - Memory Controller
Jobid 1944521
Location: San Diego, CA, 92108, USA
Job Description:
**Job Id**
E1944521
Job Title
Digital Design Engineer - Memory Controller
Post Date
04/19/2018
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
California - San Diego
Job Overview
QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The front end of the DDR controller interfaces to the rest of the system such as CPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products. The candidate will work on architecture, design, and deployment of the Memory Controllers into QCT products. You will develop or contribute to the development of design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
Minimum Qualifications
- Bachelors degree in Electrical or Computer Engineering and at least 3 years of experience in high speed digital design

Experience with the following:

- DDR controller architectures especially the front end interfacing to the CPU, DSP, and multimedia processors

- On-chip tightly coupled SRAM & L3 cache controller architecture/design

- Experience with x86 or ARM CPU/bus architectures

- Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification
Preferred Qualifications
Exposure to RTL Design Verification flows is a plus
Education Requirements
Required: Bachelor's, Computer Engineering and/or Electrical Engineering

Preferred: Master's, Computer Engineering and/or Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


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