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Design Verification Engineer

Qualcomm Inc.


Location:
Bangalore
Date:
04/25/2018
2018-04-252018-05-25
Job Code:
1961209
Qualcomm Inc.
Apply on the Company Site
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Job Details

Job Title Design Verification Engineer
Jobid 1961209
Location: Bangalore, IND
Job Description:
**Job Id**
E1961209
Job Title
Design Verification Engineer
Post Date
04/10/2018
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
India - Bangalore
Job Overview
Job Summary:


Multiple positions for 3-10 years of experience in design verification of complex Qualcomm propriety DSP IP


DSP design team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space


Qualcomm is the largest fabless design company in the world, generating over $15 Billion in annual revenues from chipsets and royalties from intellectual property. Qualcomm provides hardware, software and related services to nearly every mobile device maker and operator in the global wireless marketplace
Minimum Qualifications
Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, post silicon and back-end teams

Implement and improve System Verilog Testbench Architecture

Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency

Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals

Hand-on simulations and debug

Complete all required verification activities at IP level and insure high quality commercial success of our products

Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis

Responsible gate level simulation bring up, gate level verification with timing simulations

Responsible for power aware RTL and gate level simulation
Preferred Qualifications
3-10 years experience in processor/ASIC design verification


Solid background and understanding of Digital Design, Processor Architecture and Processor Verification


Expertise in System Verilog Testbench Architecture and implementation


Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence


Scripting/Automation Skills Perl, Python, Shell, Make file TCI


Solid analytic and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts


Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog and VHDL is preferred


Experience in AMBA, AHB, AXI, JTAG and debug protocols


Gate-Level Simulation and Debug 0-delay, timing annotated and power aware


Experience is verification of Processor subsystems (ARM/DSP) is preferred


Experience in creating validation suite and building automation


Should have excellent inter-personal and communication skills


Exposure to silicon bring up, silicon testing , bench and application testing is a definite plus
Education Requirements
Required: Bachelor's, Electrical Engineering

Preferred: Master's, Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


Apply on the Company Site
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