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DDR Verification Engineer/Lead

Qualcomm Inc.


Location:
Bangalore
Date:
04/25/2018
2018-04-252018-05-25
Job Code:
1963046
Qualcomm Inc.
Apply on the Company Site
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Job Details

Job Title DDR Verification Engineer/Lead
Jobid 1963046
Location: Bangalore, IND
Job Description:
**Job Id**
E1963046
Job Title
DDR Verification Engineer/Lead
Post Date
04/03/2018
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Verification
Location
India - Bangalore
Job Overview
Design Verification of RTL SOC/Subsystem verification of DDR (Memory controller + PHY) block.


- Good understanding of ARM CPUs and verification using C/C++/Assembly testcases.


- Hands-on experience on AMBA Bus protocols and debugging around them.


- Coherent Bridge IP cores and subsystems verification using latest verification methodologies such as System Verilog, UVM.


- Develop Functional test plans for the various functional areas and features;


- Develop constrained random verification tests and directed tests and ensure that functional coverage, code coverage and performance goals are met Develop formal verification strategy, create properties and constraints for IP cores. Working knowledge of Formal tools will be plus.


- Work with Architecture and Design Engineering teams and ensure that IP cores work as per the standard Perform gate level and back annotated timing simulations.


- Work closely with Design Engineering T
Minimum Qualifications
- 4 -12 years of experience in ASIC/SoC Design Verification including:

- Exposure to LPDDR3, LPDDR4, LPDDR5, DDR3, DDR4, DDR5 protocols & related controller/PHY designs stands highly desirable

- Experience using latest Verification methodologies such as System Verilog, and UVM.

- Experience in system bus with QOS, cache coherent bus and bridge unit verification

- Working knowledge in one or more of the following: C, C++, Python, TCL or Perl.

- Experience in scripting for automation of design methodologies & flows.

- Positive attitude and sound aptitude, willing to perform under challenging environment and ready to show ownership.
Preferred Qualifications
- 4 -12 years of experience in ASIC/SoC Design Verification including:


- Exposure to LPDDR3, LPDDR4, LPDDR5, DDR3, DDR4, DDR5 protocols & related controller/PHY designs stands highly desirable


- Experience using latest Verification methodologies such as System Verilog, and UVM.


- Experience in system bus with QOS, cache coherent bus and bridge unit verification


- Working knowledge in one or more of the following: C, C++, Python, TCL or Perl.


- Experience in scripting for automation of design methodologies & flows.


- Positive attitude and sound aptitude, willing to perform under challenging environment and ready to show ownership.
Education Requirements
B Tech/ M Tech

LI-IND*
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


Apply on the Company Site
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